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1. general description the 74ALVCH16374 is 16-bit edge-triggered flip-flop featuring separate d-type inputs for each flip-flop and 3-state outputs for bus oriented applications. incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs. the 74ALVCH16374 consists of 2 sections of eight edge-triggered flip-flops. a clock (cp) input and an output enable (oe ) are provided per 8-bit section. the flip-flops will store the state of their indivi dual d-inputs that meet the set-up and hold time requirements on the low-to-high cp transition. when oe is low, the contents of the flip-flops are available at the outputs. when oe is high, the outputs go the high-imped ance off-state. operation of the oe input does not affect the state of the flip-flops. 2. features and benefits ? wide supply voltage range from 1.2 v to 3.6 v ? complies with jedec standard jesd8-b ? cmos low power consumption ? multibyte flow-through standard pin-out architecture ? low inductance multiple v cc and gnd pins for minimum noise and ground bounce ? direct interface with ttl levels ? all data inputs have bus hold ? output drive capability 50 transmission lines at 85 c ? current drive 24 ma at v cc = 3.0 v 74ALVCH16374 2.5 v/3.3 v 16-bit edge-triggere d d-type flip-flop; 3-state rev. 03 ? 27 april 2010 product data sheet
74ALVCH16374_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 27 april 2010 2 of 17 nxp semiconductors 74ALVCH16374 2.5 v/3.3 v 16-bit edge-triggered d-type flip-flop; 3-state 3. ordering information 4. functional diagram table 1. ordering information type number temperature range package name description version 74ALVCH16374dl ? 40 c to +85 c ssop48 plastic shrink small outline package; 48 leads; body width 7.5 mm sot370-1 74lvch16374dgg ? 40 cto+85 c tssop48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362-1 fig 1. logic symbol 001aal77 0 1q0 1q1 1oe 2oe 1q2 1q3 1q4 1q5 1q6 1q7 1cp 47 46 48 25 44 43 41 40 38 37 2 3 1 5 6 8 9 11 12 24 2q0 2q1 2q2 2q3 2q4 2q5 2q6 2q7 1d0 1d1 1d2 1d3 1d4 1d5 1d6 1d7 2d0 2d1 2d2 2d3 2d4 2d5 2d6 2d7 36 35 33 32 30 29 27 26 13 14 16 17 19 20 22 23 2cp
74ALVCH16374_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 27 april 2010 3 of 17 nxp semiconductors 74ALVCH16374 2.5 v/3.3 v 16-bit edge-triggered d-type flip-flop; 3-state fig 2. iec logic symbol 001aal77 2 47 1d 1q0 1d0 2 1 46 1q1 1d1 3 44 1q2 1d2 5 43 1q3 1d3 1 1en 1oe 48 c1 1cp 24 2en 2oe 25 c2 2cp 6 41 1q4 1d4 8 40 1q5 1d5 9 38 1q6 1d6 11 37 1q7 1d7 12 36 2q0 2d0 13 35 2q1 2d1 14 33 2q2 2d2 16 32 2q3 2d3 17 30 2q4 2d4 19 29 2q5 2d5 20 27 2q6 2d6 22 26 2q7 2d7 23 2d 2 fig 3. bus hold circuit to internal circuit mna705 v cc data input fig 4. logic diagram 001aal77 1 ff1 to 7 other channels d cp q 1d0 1cp 1oe 1q0 ff9 to 7 other channels d cp q 2d0 2cp 2oe 2q0
74ALVCH16374_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 27 april 2010 4 of 17 nxp semiconductors 74ALVCH16374 2.5 v/3.3 v 16-bit edge-triggered d-type flip-flop; 3-state 5. pinning information 5.1 pinning fig 5. pin configuration 74ALVCH16374 1oe 1cp 1q0 1d0 1q1 1d1 gnd gnd 1q2 1d2 1q3 1d3 v cc v cc 1q4 1d4 1q5 1d5 gnd gnd 1q6 1d6 1q7 1d7 2q0 2d0 2q1 2d1 gnd gnd 2q2 2d2 2q3 2d3 v cc v cc 2q4 2d4 2q5 2d5 gnd gnd 2q6 2d6 2q7 2d7 2oe 2cp 001aal769 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
74ALVCH16374_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 27 april 2010 5 of 17 nxp semiconductors 74ALVCH16374 2.5 v/3.3 v 16-bit edge-triggered d-type flip-flop; 3-state 5.2 pin description 6. functional description 6.1 function table [1] h = high voltage level; l = low voltage level; h = high voltage level one set-up time pr ior to the low-to-high clock transition; i = low voltage level one set-up time prior to the low-to-high clock transition; = low-to-high clock transition; z = high-impedance off-state. table 2. pin description symbol pin description 1oe , 2oe 1, 24 output enable input (active low) 1q0 to 1q7 2, 3, 5, 6, 8, 9, 11, 12 3-state flip-flop outputs 2q0 to 2q7 13, 14, 16, 17, 19, 20 , 22, 23 3-state flip-flop outputs gnd 4, 10, 15, 21, 28, 34, 39, 45 ground (0 v) v cc 7, 18, 31, 42 positive supply voltage 1d0 to 1d7 47, 46, 44, 43, 41, 40, 38, 37 data inputs 2d0 to 2d7 36, 35, 33, 32, 30, 29, 27, 26 data inputs 1cp, 2cp 48, 25 clock input table 3. function table [1] inputs internal flip-flops outputs q0 to q7 operating mode noe ncp dn l l l l load and read register l hh h h l l z load register and disable outputs h hh z
74ALVCH16374_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 27 april 2010 6 of 17 nxp semiconductors 74ALVCH16374 2.5 v/3.3 v 16-bit edge-triggered d-type flip-flop; 3-state 7. limiting values [1] the input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] above 55 c the value of p tot derates linearly with 11.3 mw/k. [3] above 55 c the value of p tot derates linearly with 8 mw/k. 8. recommended operating conditions table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +4.6 v i ik input clamping current v i <0v ? 50 - ma v i input voltage control inputs [1] ? 0.5 +4.6 v data inputs [1] ? 0.5 v cc +0.5 v i ok output clamping current v o >v cc or v o <0v - 50 ma v o output voltage [1] ? 0.5 v cc +0.5 v i o output current v o =0v tov cc - 50 ma i cc supply current - 100 ma i gnd ground current ? 100 - ma t stg storage temperature ? 65 +150 c p tot total power dissipation t amb = ? 40 c to +125 c; ssop48 package [2] -850mw tssop48 package [3] -600mw table 5. recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage maximum speed performance c l = 30 pf 2.3 - 2.7 v c l = 50 pf 3.0 - 3.6 v low voltage applications 1.2 - 3.6 v v i input voltage data inputs 0 - v cc v control inputs 0 - 5.5 v v o output voltage 0 - v cc v t amb ambient temperature in free air ? 40 - +85 c t/ v input transition rise and fall rate v cc = 2.3 v to 3.0 v 0 - 20 ns/v v cc = 3.0 v to 3.6 v 0 - 10 ns/v
74ALVCH16374_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 27 april 2010 7 of 17 nxp semiconductors 74ALVCH16374 2.5 v/3.3 v 16-bit edge-triggered d-type flip-flop; 3-state 9. static characteristics table 6. static characteristics at recommended operating conditions. volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ [1] max unit t amb = ? 40 c to +85 c v ih high-level input voltage v cc = 1.2 v v cc --v v cc = 1.8 v 0.7v cc 0.9 - v v cc = 2.3 v to 2.7 v 1.7 1.2 - v v cc = 2.7 v to 3.6 v 2.0 1.5 - v v il low-level input voltage v cc = 1.2 v - - 0 v v cc = 1.8 v - 0.9 0.2v cc v v cc = 2.3 v to 2.7 v - 1.2 0.7 v v cc = 2.7 v to 3.6 v - 1.5 0.8 v v oh high-level output voltage v i =v ih or v il i o = ? 100 a; v cc = 1.8 v to 3.6 v v cc ? 0.2 v cc -v i o = ? 6ma; v cc = 1.8 v v cc ? 0.4 v cc ? 0.1 - v i o = ? 6ma; v cc = 2.3 v v cc ? 0.3 v cc ? 0.08 - v i o = ? 12 ma; v cc = 2.3 v v cc ? 0.5 v cc ? 0.17 - v i o = ? 12 ma; v cc = 2.7 v v cc ? 0.5 v cc ? 0.14 - v i o = ? 18 ma; v cc = 2.3 v v cc ? 0.6 v cc ? 0.26 - v i o = ? 24 ma; v cc = 3.0 v v cc ? 1.0 v cc ? 0.28 - v v ol low-level output voltage v i =v ih or v il i o = 100 a; v cc = 1.8 v to 3.6 v - 0 0.20 v i o = 6 ma; v cc = 1.8 v - 0.09 0.30 v i o =6ma; v cc = 2.3 v - 0.07 0.20 v i o =12ma; v cc = 2.3 v - 0.15 0.40 v i o =12ma; v cc = 2.7 v - 0.14 0.40 v i o = 18 ma; v cc = 2.3 v - 0.23 0.60 v i o =24ma; v cc = 3.0 v - 0.27 0.55 v i i input leakage current v cc = 1.8 v to 3.6 v control input; v i = 5.5 v or gnd - 0.1 5 a data input; v i =v cc or gnd - 0.1 5 a i oz off-state output current v i =v ih or v il ; v o =v cc or gnd v cc = 1.8 v to 2.7 v - 0.1 5 a v cc = 2.7 v to 3.6 v - 0.1 10 a i liz off-state input leakage current v i =v cc or gnd v cc = 1.8 v to 2.7 v - 0.1 10 a v cc = 3.6 v - 0.1 15 a i cc supply current v i =v cc or gnd; i o =0a; v cc = 1.8 v to 2.7 v - 0.1 20 a v cc = 2.7 v to 3.6 v - 0.2 40 a
74ALVCH16374_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 27 april 2010 8 of 17 nxp semiconductors 74ALVCH16374 2.5 v/3.3 v 16-bit edge-triggered d-type flip-flop; 3-state [1] all typical values are measured at t amb =25 c. [2] valid for data inputs of bus hold parts only. 10. dynamic characteristics i cc additional supply current v i =v cc ? 0.6 v; i o =0a; v cc =2.7v to 3.6 v per control input - 5 500 a per data i/o input - 150 750 a i bhl bus hold low current v cc = 2.3 v; v i =0.7v [2] 45 - - a v cc = 3.0 v; v i =0.8v [2] 75 150 - a i bhh bus hold high current v cc = 2.3 v; v i =1.7v [2] ? 45 - - a v cc = 3.0 v; v i =2.0v [2] ? 75 ? 175 - a i bhlo bus hold low overdrive current v cc = 2.7 v [2] 300 - - a v cc = 3.6 v [2] 450 - - a i bhho bus hold high overdrive current v cc = 2.7 v [2] ? 300 - - a v cc = 3.6 v [2] ? 450 - - a c i input capacitance - 5.0 - pf table 6. static characteristics ?continued at recommended operating conditions. volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ [1] max unit table 7. dynamic characteristics at recommended operating conditions. voltages ar e referenced to gnd (ground = 0 v); test circuit figure 9 . symbol parameter conditions min typ [1] max unit t amb = ? 40 c to +85 c f max maximum frequency see figure 6 v cc = 1.8 v 125 250 - mhz v cc = 2.3 v to 2.7 v [2] 150 300 - mhz v cc = 2.7 v 150 300 - mhz v cc = 3.0 v to 3.6 v [3] 200 350 - mhz t pd propagation delay ncp to nqn; see figure 6 [4] v cc = 1.2 v - 7.7 - ns v cc = 1.8 v 1.5 3.6 6.5 ns v cc = 2.3 v to 2.7 v [2] 1.0 2.3 4.3 ns v cc = 2.7 v 1.0 2.3 3.8 ns v cc = 3.0 v to 3.6 v [3] 1.0 2.4 3.4 ns t en enable time noe to nqn; see figure 7 [4] v cc = 1.2 v - 8.7 - ns v cc = 1.8 v 1.5 4.0 7.2 ns v cc = 2.3 v to 2.7 v [2] 1.0 2.6 4.8 ns v cc = 2.7 v 1.0 2.9 4.8 ns v cc = 3.0 v to 3.6 v [3] 1.0 2.3 4.0 ns
74ALVCH16374_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 27 april 2010 9 of 17 nxp semiconductors 74ALVCH16374 2.5 v/3.3 v 16-bit edge-triggered d-type flip-flop; 3-state [1] all typical values are measured at t amb =25 c. [2] typical values are measured at v cc = 2.5 v. [3] typical values are measured at v cc = 3.3 v. [4] t pd is the same as t plh and t phl . t en is the same as t pzl and t pzh . t dis is the same as t plz and t phz . [5] c pd is used to determine the dynamic power dissipation (p d in w). p d =c pd v cc 2 f i n+ (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts; n = number of inputs switching; (c l v cc 2 f o ) = sum of the outputs. t dis disable time noe to nqn; see figure 7 [4] v cc = 1.2 v - 6.2 - ns v cc = 1.8 v 1.5 3.1 5.4 ns v cc = 2.3 v to 2.7 v [2] 1.0 2.1 4.0 ns v cc = 2.7 v 1.0 2.9 4.5 ns v cc = 3.0 v to 3.6 v [3] 1.0 2.6 4.1 ns t w pulse width ncp high or low; see figure 6 v cc = 1.8 v 4.0 2.0 - ns v cc = 2.3 v to 2.7 v [2] 3.0 1.6 - ns v cc = 2.7 v 3.0 1.6 - ns v cc = 3.0 v to 3.6 v [3] 2.5 1.4 - ns t su set-up time dn to ncp; see figure 8 v cc = 1.8 v 1.5 0.2 - ns v cc = 2.3 v to 2.7 v [2] 1.2 0.2 - ns v cc = 2.7 v 1.5 0.4 - ns v cc = 3.0 v to 3.6 v [3] 1.2 0.2 - ns t h hold time dn to ncp; see figure 8 v cc = 1.8 v 0.6 ? 0.2 - ns v cc = 2.3 v to 2.7 v [2] 0.8 ? 0.1 - ns v cc = 2.7 v 0.6 ? 0.2 - ns v cc = 3.0 v to 3.6 v [3] 0.8 0.0 - ns c pd power dissipation capacitance per flip-flop; v i =gndtov cc [5] outputs enabled - 16 - pf outputs disabled - 10 - pf table 7. dynamic characteristics ?continued at recommended operating conditions. voltages ar e referenced to gnd (ground = 0 v); test circuit figure 9 . symbol parameter conditions min typ [1] max unit
74ALVCH16374_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 27 april 2010 10 of 17 nxp semiconductors 74ALVCH16374 2.5 v/3.3 v 16-bit edge-triggered d-type flip-flop; 3-state 11. waveforms measurement points are given in table 8 . v ol and v oh are typical output levels that occur with the output load. fig 6. propagation delay, clock input (ncp) to data output (nqn ), and pulse width 001aal7 73 v i t w t phl 1 / f max v m v m v m gnd v oh v ol ncp input nqn output t plh v m v m measurement points are given in table 8 . v ol and v oh are typical output levels that occur with the output load. fig 7. 3-state enable and disable times 001aal79 5 t plz t phz outputs disabled outputs enabled v y v x outputs enabled nqn output low-to-off off-to-low nqn output high-to-off off-to-high noe input v i v ol v oh v cc v m v m gnd gnd t pzl t pzh v m v m the shaded areas indicate when the input is per mitted to change for predictable output performance. fig 8. data setup and hold times for input (ndn) to input (ncp) 001aal7 74 v i t su t h v m v m v m gnd v i gnd ncp input ndn input t su t h v m v m v m v m
74ALVCH16374_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 27 april 2010 11 of 17 nxp semiconductors 74ALVCH16374 2.5 v/3.3 v 16-bit edge-triggered d-type flip-flop; 3-state 12. test information table 8. measurement points supply voltage input output v cc v i v m v m v x v y 2.3 v to 2.7 v and < 2.3 v v cc 0.5 0.5 v ol + 0.15 v v oh ? 0.15 v 2.7 v 2.7 v 2.7 v 1.5 v v ol + 0.3 v v oh ? 0.3 v 3.0 v to 3.6 v 2.7 v 2.7 v 1.5 v v ol + 0.3 v v oh ? 0.3 v test data is given in table 9 . definitions for test circuit: r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to output impedance z o of the pulse generator. v ext = external voltage for measuring switching times. fig 9. load circuit for measuring switching times v ext v cc v i v o mna61 6 dut c l r t r l r l g table 9. test data supply voltage input load v ext v cc v i t r , t f c l r l t plh , t phl t plz , t pzl t phz , t pzh 2.3 v to 2.7 v and < 2.3 v v cc 2.0 ns 30 pf 500 open 2 v cc gnd 2.7 v 2.7 v 2.5 ns 50 pf 500 open 2 v cc gnd 3.0 v to 3.6 v 2.7 v 2.5 ns 50 pf 500 open 2 v cc gnd
74ALVCH16374_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 27 april 2010 12 of 17 nxp semiconductors 74ALVCH16374 2.5 v/3.3 v 16-bit edge-triggered d-type flip-flop; 3-state 13. package outline fig 10. package outline sot370-1 (ssop48) unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 16.00 15.75 7.6 7.4 0.635 1.4 0.25 10.4 10.1 1.0 0.6 1.2 1.0 0.85 0.40 8 0 o o 0.18 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. sot370-1 99-12-27 03-02-19 (1) w m b p d h e e z e c v m a x a y 48 25 mo-118 24 1 a a 1 a 2 l p q detail x l (a ) 3 pin 1 index 0 5 10 mm scale s sop48: plastic shrink small outline package; 48 leads; body width 7.5 mm sot370 -1 a max. 2.8
74ALVCH16374_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 27 april 2010 13 of 17 nxp semiconductors 74ALVCH16374 2.5 v/3.3 v 16-bit edge-triggered d-type flip-flop; 3-state fig 11. package outline sot362-1 (tssop48) unit a 1 a 2 a 3 b p cd (1) e (2) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.2 0.1 8 0 o o 0.1 dimensions (mm are the original dimensions). notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. sot362-1 99-12-27 03-02-19 w m a a 1 a 2 d l p q detail x e z e c l x (a ) 3 0.25 124 48 25 y pin 1 index b h 1.05 0.85 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 1 0.25 8.3 7.9 0.50 0.35 0.8 0.4 0.08 0.8 0.4 p e v m a a t ssop48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362 -1 a max. 1.2 0 2.5 5 mm scale mo-153
74ALVCH16374_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 27 april 2010 14 of 17 nxp semiconductors 74ALVCH16374 2.5 v/3.3 v 16-bit edge-triggered d-type flip-flop; 3-state 14. abbreviations 15. revision history table 10. abbreviations acronym description cmos complementary metal-oxide semiconductor dut device under test esd electrostatic discharge hbm human body model mm machine model ttl transistor-transistor logic table 11. revision history document id release date data sheet status change notice supersedes 74ALVCH16374_3 20100427 product data sheet - 74ALVCH16374_2 modifications: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. ? table 7 ? dynamic characteristics ? : voltage ranges corrected. 74ALVCH16374_2 19980618 product specification - 74ALVCH16374_1
74ALVCH16374_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 27 april 2010 15 of 17 nxp semiconductors 74ALVCH16374 2.5 v/3.3 v 16-bit edge-triggered d-type flip-flop; 3-state 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 16.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 16.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qua lified for use in automotive applications. the product is not desi gned, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be ex pected to result in personal injury, death or severe property or environmental dam age. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer?s third party customer(s) (hereinafter both referred to as ?application?). it is customer?s sole responsibility to check whether the nxp semiconductors product is suitable and fit for the application planned. customer has to do all necessary testing for the application in order to avoid a default of the application and the product. nxp semiconducto rs does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 16.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
74ALVCH16374_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 ? 27 april 2010 16 of 17 nxp semiconductors 74ALVCH16374 2.5 v/3.3 v 16-bit edge-triggered d-type flip-flop; 3-state 17. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74ALVCH16374 2.5 v/3.3 v 16-bit edge-triggered d-type flip-flop; 3-state ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 27 april 2010 document identifier: 74ALVCH16374_3 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 functional description . . . . . . . . . . . . . . . . . . . 5 6.1 function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 recommended operating conditions. . . . . . . . 6 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 7 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 test information . . . . . . . . . . . . . . . . . . . . . . . . 11 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 15 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 16.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 17 contact information. . . . . . . . . . . . . . . . . . . . . 16 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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